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This X84161/641/129 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.
ICmic
TM
IC MICROSYSTEMS
16K/64K/128K
X84161/641/129 Port Saver EEPROM
DESCRIPTION
MPSTM EEPROM
FEATURES
*Up to 10MHz data transfer rate *25ns Read Access Time *Direct Interface to Microprocessors and Microcontrollers --Eliminates I/O port requirements --No interface glue logic required --Eliminates need for parallel to serial converters *Low Power CMOS --1.8V-3.6V, 2.5V-5.5V and 5V 10% Versions --Standby Current Less than 1A --Active Current Less than 1mA *Byte or Page Write Capable --32-Byte Page Write Mode *Typical Nonvolatile Write Cycle Time: 2ms *High Reliability --100,000 Endurance Cycles --Guaranteed Data Retention: 100 Years
The Port Saver memories need no serial ports or special hardware and connect to the processor memory bus. Replacing bytewide data memory, the Port Saver uses bytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the Port Saver provides all the serial benefits, such as low cost, low power, low voltage, and small package size while releasing I/Os for more important uses. The Port Saver memory outputs data within 25ns of an active read signal. This is less than the read access time of most hosts and provides "no-wait-state" operation. This prevents bottlenecks on the bus. With rates to 10 MHz, the Port Saver supplies data faster than required by most host read cycle specifications. This eliminates
the need for software NOPs.
The Port Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This "bit serial" interface allows the Port Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to the memory. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
BLOCK DIAGRAM
System Connection P C DSP ASIC RISC
Ports Saved
P0/CS P1/CLK P2/DI
Internal Block Diagram MPS
WP
H.V. GENERATION TIMING & CONTROL
A15
A0 D7
CE I/O
COMMAND DECODE
D0 OE WE
OE WE
AND CONTROL
X DEC
EEPROM ARRAY 16K x 8
8K x 8 2K x 8
LOGIC
P3/DO
Y DECODE DATA REGISTER
7008 FRM F02.1
(c)Xicor, Inc. 1994, 1997Patents Pending 7008-1.2 8/26/97 T2/C0/D0 SH
1
Characteristics subject to change without notice
X84161/641/129
PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:
8-LEAD PDIP 8-LEAD SOIC CE I/O WP V SS 1 2 X84161 3 X84641 4 .230 in. 8 7 6 5 V CC NC OE WE .190 in. NC VCC CE I/O 8-LEAD TSSOP 1 2 3 4 8 7 6 5 OE WE WP VSS
PIN NAMES
.114 in.
X84161
I/O CE OE WE WP
Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Write Protect Input Supply Voltage Ground No Connect
7008 FRM T01
.252 in. 20-LEAD TSSOP
14-LEAD SOIC CE I/O NC NC NC WP V SS 1 2 3 4 5 6 7 .230 in. X84129 14 13 12 11 10 9 8 V CC NC NC NC NC OE WE .390 in.
NC NC CE I/O NC NC NC WP VSS NC
1 2 3 4 5 6 7 8 9 10
X84641
20 19 18 17 16 15 14 13 12 11
NC NC VCC NC NC NC NC OE WE NC
VCC VSS
.250 in.
NC
.252 in. 28-LEAD TSSOP NC NC CE CE CE I/O NC NC NC WP VSS NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC VCC NC NC .394 in. NC NC OE WE NC NC NC
PACKAGE SELECTION GUIDE
84161 8-Lead PDIP 8-Lead SOIC 8-Lead TSSOP 8-Lead PDIP 8-Lead SOIC 20-Lead TSSOP 8-Lead PDIP 14-Lead SOIC 28-Lead TSSOP
7008 FRM T0A
84641
X84129
84129
. 252 in.
7008 FRM F01
PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby power mode. Output Enable (OE) The Output Enable input must be LOW to enable the output buffer and to read data from the device on the I/O line. Write Enable (WE) The Write Enable input must be LOW to write either data or command sequences to the device.
Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the device through the I/O pin. Write Protect (WP) When the Write Protect input is LOW, nonvolatile writes to the device are disabled. When WP is HIGH, all functions, including nonvolatile writes, operate normally. If a nonvolatile write cycle is in progress, WP going LOW will have no effect on the cycle already underway, but will inhibit any additional nonvolatile write cycles.
2
X84161/641/129
DEVICE OPERATION The X84161/641/129 are serial EEPROMs designed to interface directly with most microprocessor buses. Standard CE, OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive data and commands serially. Data Timing Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs first. Data output on the l/O line is active whenever both OE and CE are LOW. Care should be taken to ensure that WE and OE are never both LOW while CE is LOW. Read Sequence A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle between the write cycles. The address is sent serially, most significant bit first, over the I/O line. Note that this sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks on the bus whenever the device CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, writing a `1' will terminate the read sequence and enter the low power standby state, otherwise the device will await further reads in the sequential read mode. Sequential Read The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address in the array is reached, the address counter rolls over to address $0000 and reading may be continued indefinitely. Reset Sequence The reset sequence resets the device and sets an internal write enable latch. A reset sequence can be sent at any time by performing a read/write "0"/read operation (see Figs. 1 and 2). This breaks the multiple read or write cycle sequences that are normally used to read from or write to the part. The reset sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write "0" cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence (which includes the address) is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the device initiates these operations properly.
Figure 1. Read Sequence
CE
OE
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2
A1 A0
I/O (OUT) RESET
WHEN ACCESSING: X84161 ARRAY: A15-A11=0 X84641 ARRAY: A15-A13=0 X84129 ARRAY: A15-A14=0
D7 D6 D5 D4 D3 D2 D1 D0
LOAD ADDRESS
READ DATA
7008 FRM F04.1
3
X84161/641/129
Figure 2: Write Sequence
CE
OE
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
"1" "0"
I/O (OUT) RESET
WHEN ACCESSING: X84161 ARRAY: A15-A11=0 X84641 ARRAY: A15-A13=0 X84129 ARRAY: A15-A14=0
LOAD ADDRESS
LOAD DATA
START NONVOLATILE WRITE
7008 FRM F05.1
Write Sequence A nonvolatile write sequence consists of sending a reset sequence, a 16-bit address, up to 32 bytes of data, and then a special "start nonvolatile write cycle" command sequence. The reset sequence is issued first (as described in the Reset Sequence section) to set an internal write enable latch. The address is written serially by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without any read cycles between the writes. The address is sent serially, most significant bit first, on the l/O pin. Up to 32 bytes of data are written by issuing a multiple of 8 write cycles. Again, no read cycles are allowed between writes. The nonvolatile write cycle is initiated by issuing a special read/write "1"/read sequence. The first read cycle ends the page load, then the write "1" followed by a read starts the nonvolatile write cycle. The device recognizes 32byte pages (e.g., beginning at addresses XXXXXX00000 for X84161). When sending data to the part, attempts to exceed the upper address of the page will result in the address counter "wrapping-around" to the first address on the
page, where data loading can continue. For this reason, sending more than 256 consecutive data bits will result in overwriting previous data. A nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. The internal write enable latch is reset when the nonvolatile write cycle is completed and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static, with no special timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE) is HIGH. Nonvolatile Write Status The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the device. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/O pin is LOW. When the nonvolatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done.
4
X84161/641/129
Low Power Operation The device enters an idle state, which draws minimal current when: --an illegal sequence is entered. The following are the more common illegal sequences: * Read/Write/Write--any time * Read/Write `1'--When writing the address or writing data. * Write `1'--when reading data * Read/Read/Write `1'--after data is written to device, but before entering the NV write sequence. --the device powers-up; --a nonvolatile write operation completes. While a sequential read is in progress, the device remains in an active state. This state draws more current than the idle state, but not as much as during a read itself. To go back to the lowest power condition, an invalid condition is created by writing a `1' after the last bit of a read operation. Write Protection The following circuitry has been included to prevent inadvertent nonvolatile writes: --The internal Write Enable latch is reset upon power-up. --A reset sequence must be issued to set the internal write enable latch before starting a write sequence. --A special "start nonvolatile write" command sequence is required to start a nonvolatile write cycle. --The internal Write Enable latch is reset automatically at the end of a nonvolatile write cycle. --The internal Write Enable latch is reset and remains reset as long as the WP pin is LOW, which blocks all nonvolatile write cycles. --The internal Write Enable latch resets on an invalid write operation. SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
5
X84161/641/129
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ...................... -65C to +135C Storage Temperature ........................... -65C to +150C Terminal Voltage with Respect to VSS .......................................-1V to +7V DC Output Current................................................... 5mA Lead Temperature (Soldering, 10 seconds)..........300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. +70C +85C +125C
7008 FRM T02
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X84161/641/129 X84161/641/129 - 2.5 X84161/641/129 - 1.8 Limits 5V 10% 2.5V to 5.5V 1.8V to 3.6V
7008 FRM T03
Military -55C Notes: Contact factory for Military availability
D.C. OPERATING CHARACTERISTICS (VCC = 5V 10%) (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol ICC1
ICC2 ISB1 ILI ILO VlL (1) VIH (1) VOL VOH
Parameter VCC Supply Current (Read)
VCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage
Min.
Max. 1
2 1 10 10
Units mA
mA A A A V V V V
Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking @ 10MHz
ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC
-0.5 VCC x 0.7
VCC x 0.3 VCC + 0.5 0.4
IOL = 2.1mA IOH = -1mA
7008 FRM T04.2
VCC - 0.8
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
6
X84161/641/129
D.C. OPERATING CHARACTERISTICS (VCC = 2.5V to 5.5V) (Over the recommended operating conditions, unless otherwise specified.) Symbol ICC1 ICC2 ISB1 ILI ILO VlL(1) VIH(1) VOL VOH Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage VCC - 0.4 -0.5 VCC x 0.7 Limits Min. Max. 500 2 1 10 10 VCC x 0.3 VCC + 0.5 0.4 Units A mA A A A V V V V IOL = 1mA, VCC = 3V IOH = -400A, VCC = 3V
7008 FRM T05.1
Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking @ 5MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC
D.C. OPERATING CHARACTERISTICS (VCC = 1.8V to 3.6V) (Over the recommended operating conditions, unless otherwise specified.) Symbol ICC1 ICC2 ISB1 ILI ILO VlL(1) VIH(1) VOL VOH Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage VCC - 0.2 -0.5 VCC x 0.7 Limits Min. Max. 300 1 1 10 10 VCC x 0.3 VCC + 0.5 0.4 Units A mA A A A V V V V IOL = 0.5mA, VCC = 2V IOH = -250A, VCC = 2V
7008 FRM T05.1
Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking @ 3MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
7
X84161/641/129
CAPACITANCE Symbol CI/O
(2)
TA = +25C, f = 1MHz, VCC = 5V Parameter Input/Output Capacitance Input Capacitance Max. 8 6 Units pF pF Test Conditions VI/O = 0V VIN = 0V
7008 FRM T06
CIN(2)
Notes: (2) Periodically sampled, but not 100% tested.
POWER-UP TIMING Symbol tPUR
(3)
Parameter Power-up to Read Operation Power-up to Write Operation
Max. 2 5
Units ms ms
7008 FRM T07
tPUW(3)
Notes: (3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100% tested.
A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels VCC x 0.1 to VCC x 0.9 5ns VCC x 0.5
7008 FRM T08
EQUIVALENT A.C. LOAD CIRCUITS
5V 2.06K OUTPUT 3.03K 30pF 2.39K OUTPUT 4.58K 30pF 3V 2.8K OUTPUT 5.6K 30pF 2V
7008 FRM F06
7008 FRM F07
8
X84161/641/129
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits - X84161/641/129 VCC = 5V10% Symbol
tRC tCE tOE tOEL tOEH tLOW tHIGH tLZ(4) tHZ(4) tOLZ(4) tOHZ(4) tOH tWES tWEH
VCC = 2.5V - 5.5V VCC = 1.8V - 3.6V Min.
200
Parameter
Read Cycle Time CE Access Time OE Access Time OE Pulse Width OE High Recovery Time CE LOW Time CE HIGH Time CE LOW to Output In Low Z CE HIGH to Output In High Z OE LOW to Output In Low Z OE HIGH to Output In High Z Output Hold from CE or OE HIGH WE HIGH Setup Time WE HIGH Hold Time
Min.
100
Max
Max.
Min.
330
Max.
Units
ns
25 25 50 50 50 50 0 0 0 0 0 25 25 25 25 60 60 70 120 0 0 0 0 0 25 25
50 50 90 90 90 180 0 30 0 0 30 0 0 25 25
70 70
ns ns ns ns ns ns ns
35
ns ns
35
ns ns ns ns
Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs first) to the time when I/O is no longer being driven into a 5pF load. Contact factory for 10MHz X84129 availabilityRead Cycle
tRC tLOW tCE tHIGH
CE
WE
tWES tOE
t OEL
t OEH
OE
tWEH t OHZ
I/O
t OLZ t LZ
DATA
tOH t HZ
HIGH Z
7008 FRM F08
9
X84161/641/129
Write Cycle Limits - X84161/641/129 VCC = 5V 10% Symbol tNVWC(5) tWC
tWP tWPH tCS tCH tCP tCPH tOES tOEH tDS(6) tDH(6) tWPSU
(7)
VCC = 2.5V - 5.5V VCC = 1.8V - 3.6V Min. Max. 5 200
40 150 0 0 40 150 25 25 20 5 100 100
Parameter Nonvolatile Write Cycle Time Write Cycle Time
WE Pulse Width WE HIGH Recovery Time Write Setup Time Write Hold Time CE Pulse Width CE HIGH Recovery Time OE HIGH Setup Time OE HIGH Hold Time Data Setup Time Data Hold Time WP HIGH Setup WP HIGH Hold
Min.
Max. 5
Min.
Max. 5
Units ms ns
ns ns ns ns ns ns ns ns ns ns ns ns
7008 FRM T10
100
25 65 0 0 25 65 25 25 12 5 100 100
330
70 200 0 0 70 200 50 50 30 5 150 150
tWPHD(7)
Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the "start nonvolatile write cycle" sequence until the self-timed, internal nonvolatile write cycle is completed. (6) Data is latched into the X84161/641/129 on the rising edge of CE or WE, whichever occurs first. (7) Periodically sampled, but not 100% tested.
10
X84161/641/129
CE Controlled Write Cycle
tCPH tCP
CE
tOES tOEH
OE
tCS tCH tWP tWPH
WE
WP
tWPSU tDS
tWPHD tDH
I/O
DATA
tWC
HIGH Z
7008 FRM F09
WE Controlled Write Cycle
tCPH tCP
CE
tOES
OE
t CS
tCH tOEH tWP tWPH t WPHD
WE
WP
tWPSU tDS t DH
I/O
DATA
tWC
HIGH Z
7008 FRM F10
11
X84161/641/129
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) MAX.
0.325 (8.25) 0.300 (7.62)
TYP .0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
X84161/641/129
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50) X 45
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FRM F22.1
13
X84161/641/129
PACKAGING INFORMATION 14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.10) 0.010 (0.25)
0.050" T ypical
0.010 (0.25) X 45 0.020 (0.50)
0.050" Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937)
0.250"
FOOTPRINT
0.030"Typical 14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FRM F26
14
X84161/641/129
PACKAGING INFORMATION 8-LEAD PLASTIC, TSSOP PACKAGE TYPE V ,
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
15
X84161/641/129
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP P ACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.252 (6.4) .300 (6.6)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FRM F45
16
X84161/641/129
PACKAGING INFORMATION
28-LEAD PLASTIC, TSSOP P ACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.394 (10.0)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FRM F45
17
X84161/641/129
ORDERING INFORMATION X84161/641/129 Device X X G -X
VCC Range Blank = 4.5V to 5.5V, 10 MHz 2.5 = 2.5V to 5.5V, 5 MHz 1.8 = 1.8V to 3.6V, 3 MHz G = RoHS Compliant Lead-Free package Blank = Standard package. Non lead-free Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Military = -55C to +125C (contact factory)
Packages:
X84161 P = 8-Lead PDIP S8 = 8-Lead SOIC
*PART MARK CONVENTION 8-Lead TSSOP
EYWW 8161XXG
G = RoHS compliant lead free
V8 = 8-Lead TSSOP 8-Lead SOIC/PDIP Blank = 8-Lead SOIC P = 8-Lead PDIP G = RoHS compliant lead free AG = 1.8 to 3.6V, 0 to +70C AH = 1.8 to 3.6V, -40 to +85C F = 2.5 to 5.5V, 0 to +70C G = 2.5 to 5.5V, -40 to +85C
X84641 XG XX Blank = 4.5 to 5.5V, 0 to +70C I = 4.5 to 5.5V, -40 to +85C
X84641 P = 8-Lead PDIP S8 = 8-Lead SOIC
V20 = 20-Lead TSSOP
X84129 P = 8-Lead PDIP S14 = 14-Lead SOIC V28 = 28-Lead TSSOP
AG = 1.8 to 3.6V, 0 to +70C
AH = 1.8 to 3.6V, -40 to +85C F = 2.5 to 5.5V, 0 to +70C
G = 2.5 to 5.5V, -40 to +85C Blank = 4.5 to 5.5V, 0 to +70C
I = 4.5 to 5.5V, -40 to +85C
*All parts and package types not included will receive standard marking.
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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